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16.6
Operation in Clocked Synchronous Mode
Figure 16.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. One
character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one
falling edge of the synchronization clock to the next. In data reception, the SCI receives data in
synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the last-bit output state. In clocked synchronous mode, no parity or
multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication by use of a common clock. Both the transmitter and the
receiver also have a double-buffered structure, so that the next transmit data can be written during
transmission or the previous receive data can be read during reception, enabling continuous data
transfer.
Synchronization
clock
Serial data
Don't care
Note: * High except in continuous transfer
Figure 16.14 Data Format in Clocked Synchronous Communication (LSB-First)
16.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1
and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock
is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one
character, and when no transfer is performed, the clock is fixed high.
16.6.2
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize
the SCI as described in a sample flowchart in figure 16.15. When the operating mode, transfer
format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using
the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in
SSR, or RDR.
One unit of transfer data (character or frame)
*
LSB
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Rev. 1.00, 09/03, page 459 of 704
MSB
Bit 5
Bit 6
Bit 7
Don't care
*
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