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4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Exception Types and Priority
Priority Exception Type
High
Reset
1
Trace*
Direct transition*
Interrupt
Low
Trap instruction
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Not available in this LSI.
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
2
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on completion
of reset exception handling.
Started by execution of a trap instruction (TRAPA)
Trap instruction exception handling requests are accepted at
all times in program execution state.
Rev. 1.00, 09/03, page 57 of 704
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