Renesas H8S/2437 Hardware Manual page 23

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8S/2437 Group.................................................................2
Figure 1.2 Pin Assignment of H8S/2437 Group (FP-128B) ...........................................................3
Figure 1.3 Sample Design of Reset Signals without Affection Each Other..................................14
Section 2 CPU
Figure 2.1 Exception-Handling Vector Table (Normal Mode).....................................................19
Figure 2.2 Stack Structure in Normal Mode .................................................................................19
Figure 2.3 Exception-Handling Vector Table (Advanced Mode).................................................20
Figure 2.4 Stack Structure in Advanced Mode .............................................................................21
Figure 2.5 Memory Map ...............................................................................................................22
Figure 2.6 CPU Registers .............................................................................................................23
Figure 2.7 Usage of General Registers .........................................................................................24
Figure 2.8 Stack ............................................................................................................................25
Figure 2.9 General Register Data Formats (1) ..............................................................................28
Figure 2.9 General Register Data Formats (2) ..............................................................................29
Figure 2.10 Memory Data Formats...............................................................................................30
Figure 2.11 Instruction Formats (Examples) ................................................................................42
Figure 2.12 Branch Address Specification in Memory Indirect Mode .........................................46
Figure 2.13 State Transitions ........................................................................................................50
Section 3 MCU Operating Modes
Figure 3.1 Memory Map ...............................................................................................................56
Section 4 Exception Handling
Figure 4.1 Reset Sequence............................................................................................................60
Figure 4.2 Stack Status after Exception Handling ........................................................................63
Figure 4.3 Operation when SP Value is Odd ................................................................................64
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ........................................................................66
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 ................................................................76
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0.....82
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2.....84
Figure 5.5 Interrupt Exception Handling ......................................................................................86
Figure 5.6 Contention between Interrupt Generation and Disabling ............................................88
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller................................................................................92
Figure 6.2 CSn Signal Output Polarity and Output Timing........................................................100
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) .............................102
Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space) ...........................103
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space .............................................................105
Rev. 1.00, 09/03, page xxiii of xxxviii