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P44DDR
PW0S
OE0
Pin function
P44 input pin
* When the IRQ4S bit in PTCNT1 is cleared to 0, this pin functions as the IRQ4 input pin.
Note:
• P43/IRQ3/TMIX_1
When the IRQ3S bit in PTCNT1 is cleared to 0, this pin can be used as an IRQ3 pin.
The pin function is switched as shown below according to the combination of the IRQ3S bit
and the P43DDR bit.
When the external clock is selected by the CKS2 to CKS0 bits in TCR of the TMRX_1, this
pin functions as a TMCIX input pin. When the CCLR1 and CCLR0 bits in TCR of the
TMRX_1 are both set to 1, this pin functions as a TMRIX input pin.
P43DDR
Pin function
* When the IRQ3S bit in PTCNT1 is cleared to 0, this pin functions as the IRQ3 input pin.
Note:
• P42/IRQ2/TMI0_1
When the IRQ2S bit in PTCNT1 is cleared to 0, this pin can be used as an IRQ2 pin.
The pin function is switched as shown below according to the combination of the IRQ2S bit
and the P42DDR bit.
When the external clock is selected by the CKS2 to CKS0 bits in TCR of the TMR0_1, this pin
functions as a TMCI0 input pin. When the CCLR1 and CCLR0 bits in TCR of the TMR0_1
are both set to 1, this pin functions as a TMRI0 input pin.
P42DDR
Pin function
* When the IRQ2S bit in PTCNT1 is cleared to 0, this pin functions as the IRQ2 input pin.
Note:
Rev. 1.00, 09/03, page 166 of 704
0
0
P44 output pin
TMIY_1 (TMCIY/TMRIY) input pin
0
P44 input pin
TMIX_1 (TMCIX/TMRIX) input pin
0
P42 input pin
TMI0_1 (TMCI0/TMRI0) input pin
1
0
P44 output pin
IRQ4 input pin*
P44 output pin
IRQ3 input pin*
P42 output pin
IRQ2 input pin*
1
1
PW0 output pin
1
1
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