Figure 13.14 Block Diagram For Ivg Signal Generation - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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The contents of OCRA of the FRT can be updated by the automatic addition of the contents of
OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the
0 interval of the IVG signal is written to OCRAR, and a value corresponding to the 1 interval of
the IVG signal is written to OCRAF. The IVG signal is set by a compare-match after an OCRAR
addition, and reset by a compare-match after an OCRAF addition.
The IHG signal is the TMRY timer output. The TMRY is set to count internal clock pulses, and to
be cleared on a TCORA compare-match, to fix the period and set the timer output. TCORB is set
so as to reset the timer output. The IVG signal is connected as the TMRY reset input (TMRI), and
the rise of the IVG signal can be treated in the same way as a TCORA compare-match.
The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG
signal, and has an interval of 1 for 6 system clock periods.
Examples of TCR, TCSR, TCORA, and TCORB settings of the TMRY, and TCR, OCRAR,
OCRAF, and TOCR settings of the FRT are shown in table 13.10, and the IHG signal and IVG
signal timing chart is shown in figure 13.16.
Internal clock
FRC
Comparator A
CMA
Vertical
synchronization
signal generator
OCRA
OCRAR/F
IVG signal
FRT

Figure 13.14 Block Diagram for IVG Signal Generation

Rev. 1.00, 09/03, page 392 of 704

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