Tmr0 And Tmr1 Cascaded Connection; 16-Bit Count Mode; Figure 11.10 Timing Of Ovf Flag Setting - Renesas H8S/2437 Hardware Manual

φ
TCNT
Overflow signal
OVF
11.6

TMR0 and TMR1 Cascaded Connection

If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 2-system 8-bit timers are
cascaded. With this configuration, 16-bit count mode in which the TMR0 and TMR1 are used as a
single 16-bit timer or compare-match count mode in which the compare-match of the 8-bit timer
(TMR0) is counted by the TMR1 can be selected.
11.6.1

16-Bit Count Mode

When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer
with TMR0 occupying the upper eight bits and TMR1 occupying the lower 8 bits.
Setting of Compare-Match Flags:
• The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs.
• The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs.
Counter Clear Specification:
• If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare-match, the
16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match occurs.
The 16-bit counter (TCNT0 and TCNT1 together) is also cleared when counter clear by the
TMI0 pin has been set.
• The settings of the CCLR1 and CCLR0 bits in TCR1 are invalid. The lower 8 bits cannot be
cleared independently.
Pin Output:
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the
16-bit compare-match conditions.
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the
lower 8-bit compare-match conditions.
H'FF

Figure 11.10 Timing of OVF Flag Setting

H'00
Rev. 1.00, 09/03, page 287 of 704