Figure 6.8 Bus Timing For 16-Bit, 2-State Access Space (Odd Byte Access) - Renesas H8S/2437 Hardware Manual

Bus cycle
T 1 T 2
Address bus
D15 to D8 Invalid
Read
D7 to D0 Valid
High
Write
D15 to D8
Undefined
D7 to D0
Valid
Note: n = 1 to 3

Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)

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