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11.6.2
Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts the occurrence of compare-match A
for the TMR0. The TMR0 and TMR1 are controlled independently. Conditions such as setting of
the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for the TMR0 and TMR1.
11.7
TMRY and TMRX Cascaded Connection
If bits CKS2 to CKS0 in either TCRY or TCRX are set to B'100, the 2-system 8-bit timers are
cascaded. With this configuration, 16-bit count mode in which the TMRY and TMRX are used as
a single 16-bit timer or compare-match count mode in which the compare-match of the 8-bit timer
(TMRY) is counted by the TMRX can be selected.
11.7.1
16-Bit Count Mode
When bits CKS2 to CKS0 in TCRY are set to B'100, the timer functions as a single 16-bit timer
with TMRY occupying the upper eight bits and TMRX occupying the lower 8 bits.
Setting of Compare-Match Flags:
• The CMF flag in TCSRY is set to 1 when an upper 8-bit compare-match occurs.
• The CMF flag in TCSRX is set to 1 when a lower 8-bit compare-match occurs.
Counter Clear Specification:
• If the CCLR1 and CCLR0 bits in TCRY have been set for counter clear at compare-match,
only the upper eight bits of TCNTY are cleared. The upper eight bits of TCNTY are also
cleared when counter clear by the TMRIY pin has been set.
• The settings of the CCLR1 and CCLR0 bits in TCRX are valid, and the lower 8 bits of
TCNTX can be cleared.
Pin Output:
• Control of output from the TMOY pin by bits OS3 to OS0 in TCSRY is in accordance with the
upper 8-bit compare-match conditions.
• Control of output from the TMOX pin by bits OS3 to OS0 in TCSRX is in accordance with the
lower 8-bit compare-match conditions.
Rev. 1.00, 09/03, page 288 of 704
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