C Bus Interrupt Enable Register (Icier) - Renesas H8S/2437 Hardware Manual

Bit Bit Name Initial Value R/W
2 BC2 0
1 BC1 0
0 BC0 0
2
17.3.4 I

C Bus Interrupt Enable Register (ICIER)

ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transmitted, and confirms acknowledge bits to be received.
Bit Bit Name Initial Value R/W
7 TIE 0
6 TEIE 0
Description
R/W Bit Counter 2 to 0
R/W Specify the number of bits to be transferred next. The data
is transferred with one acknowledge bit added. BC2 to BC0
R/W
settings should be made during an interval between
transfer frames. If bits BC2 to BC0 are set to a value other
than 000, the setting should be made while the SCL signal
is low. The value automatically returns to B'000 at the end
of a data transfer, including the acknowledge bit.
000: 9 bits
001: 2 bits
010: 3 bits
011: 4 bits
100: 5 bits
101: 6 bits
110: 7 bits
111: 8 bits
Description
R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
R/W Transmit End Interrupt Enable
Enables or disables the transmit end interrupt (TEI) at the
rising of the ninth clock while the TDRE bit in ICSR is 1.
The TEI can be canceled by clearing the TEND bit or the
TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Rev. 1.00, 09/03, page 483 of 704