Slave Address Register B (Sarb); Slave Address Mask Register (Samr) - Renesas H8S/2437 Hardware Manual

17.3.8

Slave Address Register B (SARB)

SARB sets slave addresses. When the chip is in slave mode, if the upper 7 bits in SARB match the
upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Bit Bit Name Initial Value R/W Description
7 to 1 SVA6 to All 0
SVA0
0 SARE 0
17.3.9

Slave Address Mask Register (SAMR)

SAMR masks slave addresses set in SAR and controls automatic switching of transmit modes in
slave mode.
Bit Bit Name Initial Value R/W
7 MSA6 0
6 MSA5 0
5 MSA4 0
4 MSA3 0
3 MSA2 0
2 MSA1 0
1 MSA0 0
0 MTRS 0
Rev. 1.00, 09/03, page 488 of 704
R/W Slave Address 6 to 0
Set a unique address in bits SVA6 to SVA0, differing from
the addresses of other slave devices connected to the I
bus.
R/W Slave Address Enable
Selects whether slave addresses in SARB are recognized
or not.
0: Ignores slave addresses in SARB
1: Recognizes slave addresses in SARB
Description
R/W Slave Address Mask 6 to 0
R/W Correspond to the SVA6 to SVA0 bits in SAR and control
comparison conditions for addresses set in SAR and
R/W
addresses of upper 7 bits of the first frame received after a
R/W
start condition in slave mode.
R/W
0: Compare addresses set in bits SVA6 to SVA0 in SAR
and receive addresses
R/W
1: Operate assuming that receive addresses have matched
R/W
bits SVA6 to SVA0 in SAR
R/W Transmit Mode Switch Mask
Controls automatic switching of transmit modes by the
eighth bit of the first frame in slave mode.
0: When the eighth bit of the first frame is 1, the TRS bit in
ICCRA and TDRE bit in ICSR are automatically set to 1
and a transition is made to slave transmit mode.
1: The TRS bit in ICCRA and TDRE bit in ICSR are not
automatically changed by the eighth bit of the first
frame.
2
C