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• P63/TMOY_1/D3
The pin function is switched as shown below according to the combination of the operating
mode, the OS3 to OS0 bits in TCSR of the TMRY_1, and the P63DDR bit.
• Extended Mode (EXPE = 1)
Bus width*
OS3 to OS0
P63DDR
Pin function
Note:
* When the ABW3 to ABW1 bits in BCRA3 to BCRA1 are all set to 1, bus width is 8 bits,
if any are cleared to 0, bus width is 16 bits.
• Single-Chip Mode (EXPE = 0)
OS3 to OS0
P63DDR
Pin function
• P62/TMOX_1/D2
The pin function is switched as shown below according to the combination of the operating
mode, the OS3 to OS0 bits in TCSR of the TMRX_1, and the P62DDR bit.
• Extended Mode (EXPE = 1)
Bus width*
OS3 to OS0
P62DDR
Pin function
Note:
* When the ABW3 to ABW1 bits in BCRA3 to BCRA1 are all set to 1, bus width is 8 bits,
if any are cleared to 0, bus width is 16 bits.
• Single-Chip Mode (EXPE = 0)
OS3 to OS0
P62DDR
Pin function
Normal Extended Mode (ADMXE = 0)
16-bit
D3 I/O pin
All 0
0
P63 input pin
Normal Extended Mode (ADMXE = 0)
16-bit
D2 I/O pin
All 0
0
P62 input pin
8-bit
Single-chip operation
1
P63 output pin
8-bit
Single-chip operation
1
P62 output pin
Multiplex Extended Mode
(ADMXE = 1)
Single-chip operation
At least one bit is set to 1
TMOY_1 output pin
Multiplex Extended Mode
(ADMXE = 1)
Single-chip operation
At least one bit is set to 1
TMOX_1 output pin
Rev. 1.00, 09/03, page 179 of 704
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