Pwm Modes; Figure 12.22 Example Of Cascaded Operation (1); Figure 12.23 Example Of Cascaded Operation (2) - Renesas H8S/2437 Hardware Manual

TCNT_1
clock
TCNT_1 H'03A1
TCNT_2
clock
TCNT_2 H'FFFF
TIOCA1,
TIOCA2
TGRA_1
TGRA_2
Figure 12.23 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
TCNT_1
12.5.5

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
Rev. 1.00, 09/03, page 338 of 704
H'0000

Figure 12.22 Example of Cascaded Operation (1)

FFFD FFFE FFFF 0000
0000

Figure 12.23 Example of Cascaded Operation (2)

H'03A2
H'03A2
H'0000
0001 0002 0001
0001
H'0001
0000 FFFF
0000