C Bus Control Register A (Iccra) - Renesas H8S/2437 Hardware Manual

2
17.3.1 I

C Bus Control Register A (ICCRA)

ICCRA enables or disables the I
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit Bit Name Initial Value R/W
7 ICE 0
6 RCVD 0
5 MST 0
4 TRS 0
3 CKS3 0
2 CKS2 0
1 CKS1 0
0 CKS0 0
2
C bus interface, controls transmission or reception, and selects
Description
2
R/W I C Bus Interface Enable
0: This module is halted.
1: This module is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
R/W Reception Disable
Enables or disables the next operation when TRS is 0 and
ICDRR is read.
0: Enables next reception
1: Disables next reception
R/W Master/Slave Select
R/W Transmit/Receive Select
When arbitration is lost in master mode, MST and TRS are
both reset by hardware, causing a transition to slave
receive mode. Modification of the TRS bit should be made
between transfer frames.
Operating modes are described below according to MST
and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
R/W Transfer Clock Select 3 to 0
R/W
These bits are valid only in master mode and should be set
R/W
according to the necessary transfer rate. For details on
R/W
transfer rate, see table 17.2.
Rev. 1.00, 09/03, page 479 of 704