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6.4.4
Address Strobe/Hold Signal
In normal extended mode, the address above the bus address is enabled, which is indicated by the
output strobe signal (AS). In multiplex extended mode, the hold signal (AH) which indicates the
address fetch timing, is output. Output polarity of the AS/ AH signals can be controlled by the
PNCASH bit in BCR.
6.4.5
Address Output
This LSI can output a maximum of 16 addresses.
In normal extended mode, enabling or disabling of A15 to A0 signal output is set by the data
direction register (DDR) bit for the port corresponding to the A15 to A0 pins. In external extended
mode, the A15 to A0 pins are placed in the input state after a reset, the corresponding DDR bits
should be set to 1 when outputting signals A15 to A0. For details, refer to section 7, I/O Ports.
In multiplex extended mode, the address output is decided by the access area bus width. If the
access area is 16 bits, the lower 16-bit internal addresses are output from A15 to A0 in the address
cycle. If the access area is 8 bits, the lower 8-bit internal addresses are output from A15 to A8 in
the address cycle.
Rev. 1.00, 09/03, page 101 of 704
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