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15.2
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCNT and TCSR have
to be written to in a method different from normal registers. For details, see section 15.5.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
15.2.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in the timer control/status register (TCSR) is
cleared to 0.
15.2.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit
Bit Name Initial Value R/W
7
OVF
0
6
WT/IT
0
Rev. 1.00, 09/03, page 418 of 704
Description
R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, this bit is cleared automatically by
the internal reset.
[Clearing conditions]
•
When TCSR is read when OVF = 1, then 0 is written
to OVF
•
When 0 is written to TME
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
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