Table 12.19 Pwm Output Registers And Output Pins - Renesas H8S/2437 Hardware Manual

PWM Mode 1:
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The value specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the value specified by
bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial
output value is the value set in TGRA or TGRC. When the set values of paired TGRs are identical,
the output value does not change even if a compare match occurs.
In PWM mode 1, a maximum 4-phase PWM output is possible.
PWM Mode 2:
PWM output is generated using one TGR as the periodic register and the others as duty registers.
The value specified in TIOR is output by means of compare matches. Upon counter clearing by a
synchronous register compare match, the output value of each pin is the initial value set in TIOR.
When the set values of the periodic and duty registers are identical, the output value does not
change even if a compare match occurs.
In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with synchronous
operation.
The correspondence between PWM output pins and registers is shown in table 12.19.

Table 12.19 PWM Output Registers and Output Pins

Channel
0
1
2
Note: In PWM mode 2, PWM output is not possible for TGR in which the period is set.
Registers
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
Output Pins
PWM Mode 1
TIOCA0
TIOCC0
TIOCA1
TIOCA2
Rev. 1.00, 09/03, page 339 of 704
PWM Mode 2
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2