Figure 6.23 Bus Timing For 16-Bit, 3-State Data Access Space - Renesas H8S/2437 Hardware Manual

T
AD15 to AD8
AD7 to AD0
Note: n = 1 to 3

Figure 6.23 Bus Timing for 16-Bit, 3-State Data Access Space (2)

Read Cycle
Data
Address
T T T T
1 AW 2 3
Address
Address
(Odd Byte Access, with Address Wait)
Address
T T
T T
4 DSW 5 1
Address
Data Address
Write Cycle
Data
T T T T
AW 2 3 4
Data
Rev. 1.00, 09/03, page 123 of 704
T
DSW 5