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• P24/TIOCA1/A12/AD12
When the TIOCA1S bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCA1 pin.
According to operating modes, the TPU channel 1 settings by the MD3 to MD0 bits in
TMDR_1, the IOA3 to IOA0 bits in TIOR_1, and the CCLR1 and CCLR0 bits in TCR_1, and
the combination of the TIOCA1S bit and the P24DDR bit, pin functions change as follows.
• Extended Mode (EXPE = 1)
Normal Extended Mode (ADMXE = 0)
P24DDR
Pin function
P24 input pin
• Single-Chip Mode (EXPE = 0)
TIOCA2S
TPU channel
1 setting
P24DDR
Pin function
P24 input pin
TPU channel
1 setting
MD3 to MD0
IOA3 to IOA0
B'0000
B'0100
B'1xxx
CCLR1,
CCLR0
Output
function
[Legend]
x: Don't care
Notes: 1. When TIOCA1S = 0, MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx, this
pin functions as the TIOCA1 input pin.
2. Output is disabled for TIOCB1.
0
A12 output pin
0
Table below (2)
0
1
P24 output pin
1
TIOCA1 input pin*
(2)
(1)
B'0000, B'01xx
B'0001 to B'0011
B'0101 to B'0111
Output compare
output
Multiplex Extended Mode (ADMXE = 1)
1
1
TIOCA1 input pin*
Table below (1)
TIOCA1 output
pin
(2)
(1)
B'001x
B'0010
B'xx00
Other than
B'xx00
PWM*
mode 1
output
Rev. 1.00, 09/03, page 149 of 704
AD12 I/O pin
1
0
P24 input pin
P24 output pin
(1)
B'0011
Other than B'xx00
Other than
B'01
2
PWM
mode 2
output
1
(2)
B'01
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