Figure 17.14 Sample Flowchart For Master Transmit Mode - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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Start
Initialize
Read BBSY in ICCRB
No
BBSY = 0 ?
Yes
Set MST = 1 and TRS
= 1 in ICCRA
Write BBSY = 1
and SCP = 0
Write transmit data
to ICDRT
Read TEND in ICSR
No
TEND = 1 ?
Yes
Read ACKBR in ICIER
No
ACKBR = 0 ?
Yes
No
Transmit
mode?
Yes
Write transmit data to ICDRT
Read TDRE in ICSR
No
TDRE = 1 ?
Yes
No
Last byte?
Yes
Write transmit data to ICDRT
Read TEND in ICSR
No
TEND = 1 ?
Yes
Clear TEND in ICSR
Clear STOP in ICSR
Write BBSY = 0
and SCP = 0
Read STOP in ICSR
No
STOP = 1 ?
Yes
Set MST = 0 and TRS
= 0 in ICCRA
Clear TDRE in ICSR
End

Figure 17.14 Sample Flowchart for Master Transmit Mode

[1]
[1]
Test the status of the SCL and SDA lines.
[2]
Set master transmit mode.
[2]
[3]
Start condition issuance.
[3]
[4]
Set transmit data for the first byte (slave address + R/W).
[5]
Wait for 1 byte to be transmitted.
[4]
[6]
Test the acknowledge bit, transferred from the specified slave device.
[7]
Set transmit data for the second and subsequent data (except for the last byte).
[5]
[8]
Wait for ICDRT empty.
[9]
Set transmit data for the last byte.
[6]
[10] Wait for the completion of transmission for the last byte.
[11] Clear TEND flag.
Master receive mode
[12] Clear STOP flag.
[7]
[13] Stop condition issuance.
[14] Wait for the generation of the stop condition.
[8]
[15] Set slave receive mode. Clear TDRE.
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Rev. 1.00, 09/03, page 501 of 704

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