Table 12.12 Tiorl_0 (Channel 0) - Renesas H8S/2437 Hardware Manual

Table 12.12 TIORL_0 (Channel 0)

Bit 3 Bit 2
IOC3 IOC2
0 0
1
1 0
1
[Legend] x: Don't care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 1.00, 09/03, page 314 of 704
Bit 1 Bit 0
IOC1 IOC0
0 0
1
1 0
1
0 0
1
1 0
1
0 0
1
×
1
× ×
TGRC_0
Function TIOCC0 Pin Function
Output Output disabled
compare
Initial output is 0 output
register*
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Input capture Capture input source is TIOCC0 pin
register* Input capture at rising edge
Capture input source is TIOCC0 pin
Input capture at falling edge
Capture input source is TIOCC0 pin
Input capture at both edges
Capture input source is channel
1/count clock
Input capture at TCNT_1 count-
up/count-down
Description