φ
A15 to A0,
(Read)
D15 to D0
(Read)
(Write)
D15 to D0
(Write)
Rev. 1.00, 09/03, page 678 of 704
T 1
t
AD
to
t
t
AS
CSD
t
t
AS
t
,
t
AS
t
Figure 24.8 Basic Bus Timing/2-State Access
T 2
t
ASD
ASD
t
t
RSD1
ACC2
t
ACC3
t
WRD2
WRD2
t
WSW1
WDD
t
AH
t
RSD2
t
t
RDS
RDH
t
AH
t
WDH