Renesas H8S/2437 Hardware Manual page 30

Figure 20.9 Overview of Programming/Erasing Flow................................................................ 555
Figure 20.10 RAM Map when Programming/Erasing is Executed ............................................ 556
Figure 20.11 Programming Procedure........................................................................................ 557
Figure 20.12 Erasing Procedure.................................................................................................. 562
Figure 20.13 Repeating Procedure of Erasing and Programming............................................... 564
Figure 20.14 Procedure for Programming User MAT in User Boot Mode ................................ 566
Figure 20.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 567
Figure 20.16 Transitions to Error Protection State ..................................................................... 580
Figure 20.17 Switching between User MAT and User Boot MAT ............................................ 581
Figure 20.18 Memory Map in Programmer Mode...................................................................... 582
Figure 20.19 Boot Program States .............................................................................................. 584
Figure 20.20 Bit-Rate-Adjustment Sequence ............................................................................. 585
Figure 20.21 Communication Protocol Format .......................................................................... 586
Figure 20.22 New Bit-Rate Selection Sequence ......................................................................... 596
Figure 20.23 Programming Sequence......................................................................................... 599
Figure 20.24 Erasure Sequence .................................................................................................. 602
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator ............................................................... 611
Figure 21.2 Typical Connection to Crystal Resonator................................................................ 614
Figure 21.3 Equivalent Circuit of Crystal Resonator.................................................................. 614
Figure 21.4 Example of External Clock Input ............................................................................ 615
Figure 21.5 External Clock Input Timing................................................................................... 616
Figure 21.6 Timing of Output Stabilization Delay Time for External Clock ............................. 616
Figure 21.7 Note on Board Design of Oscillation Circuit Section............................................... 617
Section 22 Power-Down Modes
Figure 22.1 Mode Transitions..................................................................................................... 621
Figure 22.2 Software Standby Mode Application Example ....................................................... 629
Figure 22.3 Hardware Standby Mode Timing ............................................................................ 631
Section 24 Electrical Characteristics
Figure 24.1 Darlington Transistor Drive Circuit (Example)....................................................... 672
Figure 24.2 Output Load Circuit................................................................................................. 673
Figure 24.3 System Clock Timing .............................................................................................. 674
Figure 24.4 Oscillation Stabilization Timing.............................................................................. 674
Figure 24.5 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 675
Figure 24.6 Reset Input Timing .................................................................................................. 676
Figure 24.7 Interrupt Input Timing............................................................................................. 676
Figure 24.8 Basic Bus Timing/2-State Access............................................................................ 678
Figure 24.9 Basic Bus Timing/3-State Access............................................................................ 679
Figure 24.10 Basic Bus Timing/3-State Access with One Wait State ........................................ 680
Figure 24.11 Muliplex Bus Timing/2-State Access.................................................................... 682
Figure 24.12 Multiplex Bus Timing/3-State Access................................................................... 683
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