Renesas H8S/2437 Hardware Manual page 267

• DADRB
Bit Bit Name Initial Value
15 DA13 1
14 DA12 1
13 DA11 1
12 DA10 1
11 DA9 1
10 DA8 1
9 DA7 1
8 DA6 1
7 DA5 1
6 DA4 1
5 DA3 1
4 DA2 1
3 DA1 1
2 DA0 1
1 CFS 1
0 REGS 1
R/W Description
R/W D/A Data 13 to 0
R/W
Set a digital value to be converted to an analog value.
R/W
In each base cycle, the DACNT value is continually
R/W
compared with the DADR value to determine the duty
R/W
cycle of the output waveform, and to decide whether to
R/W
output a fine-adjustment pulse equal in width to the
R/W
resolution. To enable this operation, this register must
R/W
be set within a range that depends on the CFS bit. If the
R/W
DADR value is outside this range, the PWM output is
R/W
fixed.
R/W
R/W
A channel can be operated with 12-bit accuracy by
R/W
fixing DA0 and DA1 to 0. The lower two data bits are
R/W
not compared with UC12 and UC13 in DACNT.
R/W Carrier Frequency Select
0: Base cycle = resolution (T) × 64
The range of DA13 to DA0: H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
The range of DA13 to DA0: H'0040 to H'3FFF
R/W Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed. When changing the
register to be accessed, set this bit in advance.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Rev. 1.00, 09/03, page 229 of 704