Figure 6.18 Bus Timing For 16-Bit, 2-State Access Space (3) (Odd Byte Access, With Address Wait) - Renesas H8S/2437 Hardware Manual

AD15 to AD8
AD7 to AD0
Note: n = 1 to 3
Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3)
Rev. 1.00, 09/03, page 118 of 704
Read Cycle
Address Data
T T T T
1 AW 2 3
Address
Address
(Odd Byte Access, with Address Wait)
Write Cycle
Address
T T T T
4 1 AW 2
Address
Address
Data
Data
T T
3 4
Data