Table 13.2 Synchronization Signal Connection Enable - Renesas H8S/2437 Hardware Manual

Bit Bit Name
1 HIINV
0 VIINV

Table 13.2 Synchronization Signal Connection Enable

Bit 5
SCONE Mode FTIA
0 Normal FTIA
connection input
(Initial
value)
1 Synchroniza IVI
-tion signal signal
connection
mode
Note: * Only FTIC input is available in channel 1.
Initial Value R/W
0 R/W
0 R/W
FTIB FTIC
FTIB FTIC
input input
TMO1 VFBACKI
signal input*
Description
Horizontal and Composite Synchronization Signal
Inversion
Selects inversion of the input phase of the horizontal
synchronization signal (HSYNCI) and composite
synchronization signal (CSYNCI).
0: The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
1: The HSYNCI and CSYNCI pin states are inverted
before use as the HSYNCI and CSYNCI inputs
Vertical Synchronization Signal Inversion
Selects inversion of the input phase of the vertical
synchronization signal (VSYNCI).
0: The VSYNCI pin state is used directly as the
VSYNCI input
1: The VSYNCI pin state is inverted before use as
the VSYNCI input
Description
FTID TMCI1
FTID TMI1
input input
IHI IHI
signal signal
Rev. 1.00, 09/03, page 371 of 704
TMRI1 TMCIX TMRIX
TMI1 TMIX TMIX
input input input
IVI IHI signal IHI signal
inverse
signal