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22.2
Operation
22.2.1
Clock Division Mode
When the SCK2 to SCK0 bits in SCKCR are set to a value from B'001 to B'010, a transition is
made to clock division mode. In clock division mode, the CPU and on-chip peripheral functions
all operate on the operating clock (1/2 or 1/4) specified by bits SCK2 to SCK0.
Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode at the end of the bus cycle, and clock division mode is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external interrupt, clock
division mode is restored.
When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by a watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.
22.2.2
Sleep Mode
Transition to Sleep Mode:
When the SLEEP instruction is executed when the SSBY bit is 0 in SBYCR, the CPU enters sleep
mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are
retained. Other peripheral functions do not stop.
Exiting Sleep Mode:
Sleep mode is exited by any interrupt, or signals at the RES or STBY pin.
• Exiting Sleep Mode by Interrupts
When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exiting Sleep Mode by RES pin
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high starts the CPU performing reset exception handling.
Rev. 1.00, 09/03, page 626 of 704
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