Figure 12.35 Output Compare Output Timing; Figure 12.36 Input Capture Input Signal Timing - Renesas H8S/2437 Hardware Manual

Output Compare Output Timing:
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output (TIOC) pin. After a
match between TCNT and TGR, the compare match signal is not generated until the TCNT input
clock is generated. Figure 12.35 shows output compare output timing.
φ
TCNT
input clock
TCNT
TGR
Compare
match signal
TIOC pin
Input Capture Signal Timing:
Figure 12.36 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
N
N

Figure 12.35 Output Compare Output Timing

N

Figure 12.36 Input Capture Input Signal Timing

N+1
N+1 N+2
N
Rev. 1.00, 09/03, page 351 of 704
N+2