Timer Control/Status Register (Tcsr) - Renesas H8S/2437 Hardware Manual

11.3.5

Timer Control/Status Register (TCSR)

TCSR indicates the status flags and controls compare-match output.
• TCSR0
Bit Bit Name Initial Value R/W
7 CMFB 0
6 CMFA 0
5 OVF 0
4 ADTE 0
3 OS3 0
2 OS2 0
Description
1
R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT0 and TCORB0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 to CMFB
1
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT0 and TCORA0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 to CMFA
1
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT0 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 to OVF
R/W A/D Trigger Enable*
Enables or disables A/D conversion start requests by
compare-match A.
0: A/D converter start requests by compare-match A
are disabled
1: A/D converter start requests by compare-match A
are enabled
R/W Output Select 3, 2
R/W Specify how the TMO0 pin output level is to be
changed by compare-match B of TCORB0 and TCNT0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
2
Rev. 1.00, 09/03, page 277 of 704