Register Description; System Clock Control Register (Sckcr) - Renesas H8S/2437 Hardware Manual

21.1

Register Description

The clock pulse generator has the following register.

• System clock control register (SCKCR)

21.1.1 System Clock Control Register (SCKCR)
SCKCR controls φ output and selects the division ratio for the divider.
Bit Bit Name
7 PSTOP

6 to 3
Rev. 1.00, 09/03, page 612 of 704
Initial Value R/W
0 R/W
All 0 R/W
Description
φ Output Disabled
Controls φ output.
In normal operation:
0: φ output
1: Fixed to high
In sleep mode:
0: φ output
1: Fixed to high
In software standby mode:
0: Fixed to high
1: Fixed to high
In hardware standby mode:
0: High impedance
1: High impedance
Reserved
Although these bits are readable/writable, only 0
should be written here.