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2.8
Processing States
The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
• Reset State
The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes
low, all current processing stops and the CPU enters the reset state. All interrupts are masked
in the reset state. Reset exception handling starts when the RES signal changes from low to
high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception-handling vector table and
branches to that address. For further details, refer to section 4, Exception Handling.
• Program Execution State
In this state the CPU executes program instructions in sequence.
• Bus-Released State
In a product which has a bus mastership other than the CPU, such as a direct memory access
controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when
the bus has been released in response to a bus request from a bus mastership other than the
CPU. While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, refer to section 22, Power-Down Modes.
Rev. 1.00, 09/03, page 49 of 704
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