Figure 1.3 Sample Design Of Reset Signals Without Affection Each Other - Renesas H8S/2437 Hardware Manual

Notes: 1. Not supported by the on-chip emulator.
2. Following precautions are required on the power-on reset signal that is applied to the
ETRST pin.
The reset signal must be applied at a power-on.
Apart the power-on reset circuit from this LSI to prevent the ETRST pin of the board
tester from affecting the operation of this LSI.
Apart the power-on reset circuit from this LSI to prevent the system reset of this LSI
from affecting the ETRST pin of the board tester.
Figure1.3 shows an example of design in which signals for reset do not affect each other.
Board edge pin
System
reset

Figure 1.3 Sample Design of Reset Signals without Affection Each Other

Rev. 1.00, 09/03, page 14 of 704
Power-on
reset circuit
This LSI