Table of Contents
Advertisement
12.3.9 Timer Synchro Register (TSYR) ......................................................................... 324
12.4 Interface to Bus Master ..................................................................................................... 325
12.4.1 16-Bit Registers ................................................................................................... 325
12.4.2 8-Bit Registers ..................................................................................................... 325
12.5 Operation .......................................................................................................................... 327
12.5.1 Basic Functions.................................................................................................... 327
12.5.2 Synchronous Operation........................................................................................ 332
12.5.3 Buffer Operation .................................................................................................. 334
12.5.4 Cascaded Operation ............................................................................................. 337
12.5.5 PWM Modes ........................................................................................................ 338
12.5.6 Phase Counting Mode.......................................................................................... 343
12.6 Interrupt Sources............................................................................................................... 348
12.6.1 Interrupt Source and Priority ............................................................................... 348
12.6.2 A/D Converter Activation.................................................................................... 349
12.7 Operation Timing.............................................................................................................. 350
12.7.1 Input/Output Timing ............................................................................................ 350
12.7.2 Interrupt Signal Timing........................................................................................ 354
12.8 Usage Notes ...................................................................................................................... 357
Section 13 Timer Connection ............................................................................365
13.1 Features............................................................................................................................. 365
13.2 Input/Output Pins .............................................................................................................. 368
13.3 Register Descriptions ........................................................................................................ 369
13.3.1 Timer Connection Register I (TCONRI) ............................................................. 369
13.3.2 Timer Connection Register O (TCONRO) .......................................................... 372
13.3.3 Timer Connection Register S (TCONRS)............................................................ 375
13.3.4 Edge Sense Register (SEDGR) ............................................................................ 377
13.3.5 Timer Extended Control Register (TECR) .......................................................... 379
13.4 Operation .......................................................................................................................... 380
13.4.1 PWM Decoding (PDC Signal Generation) .......................................................... 380
13.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 382
13.4.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 385
13.4.4 2fH Modification of IHI Signal ........................................................................... 387
13.4.5 IVI Signal Fall Modification and IHI Synchronization ....................................... 389
(IHG/IVG/CL4 Signal Generation) ..................................................................... 391
13.4.7 HSYNCO Output................................................................................................. 396
13.4.8 VSYNCO Output................................................................................................. 397
13.4.9 CBLANK Output................................................................................................. 398
Rev.1.00, 09/03, page xvi of xxxviii
Advertisement
Table of Contents
