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21.2.2
External Clock Input Method
Figure 21.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin
open, parasitic capacitance should be 10 pF or less.
To input an inverted clock to the XTAL pin, the external clock should be set to high in standby
mode. External clock input conditions are shown in table 21.3.
(b) Example of external clock input when an inverted clock is input to XTAL pin
Table 21.3 External Clock Input Conditions
Item
External clock input
pulse width low level
External clock input
pulse width high level
External clock rising
time
External clock falling
time
Clock pulse width low
level
Clock pulse width high
level
EXTAL
XTAL
(a) Example of external clock input when XTAL pin left open
EXTAL
XTAL
Figure 21.4 Example of External Clock Input
VCC = 3.0 to 3.6 V
Symbol Min.
t
15
EXL
t
15
EXH
t
EXr
t
EXf
t
0.4
CL
t
0.4
CH
External clock input
Open
External clock input
Max.
Unit
Test Conditions
ns
Figure 21.5
ns
5
ns
5
ns
0.6
t
Figure 24.3
cyc
0.6
t
cyc
Rev. 1.00, 09/03, page 615 of 704
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