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12.5.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the settings of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, since the functions of bits CCLR1 and CCLR0 in TCR,
and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions
can be used.
When an overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when an
underflow occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 12.20 shows the correspondence between external clock pins and channels.
Table 12.20 Clock Input Pins for Phase Counting Mode
Channels
When channel 1 is set to phase counting mode
When channel 2 is set to phase counting mode
Example of Setting Procedure for Phase Counting Mode:
Figure 12.28 shows an example of the setting procedure for phase counting mode.
Phase counting mode
Select phase counting mode
<Phase counting mode>
Figure 12.28 Example of Setting Procedure for Phase Counting Mode
[1]
[2]
Start counting
External Clock Pins
A-Phase
TCLKA
TCLKC
[1]
Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2]
Set the CST bit in TSTR to 1 to start the count
operation.
Rev. 1.00, 09/03, page 343 of 704
B-Phase
TCLKB
TCLKD
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