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16.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared.
Bit
Bit Name
7
TDRE
6
RDRF
5
ORER
Initial Value
R/W
1
R/(W)* Transmit Data Register Empty
0
R/(W)* Receive Data Register Full
0
R/(W)* Overrun Error
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR
and TDR is ready for data write
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE
= 1
•
When data is written to TDR
Indicates whether receive data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading
RDRF = 1
•
When data is read from RDR
The RDRF flag is not affected and retains its
previous value even if the RE bit in SCR is cleared
to 0.
[Setting condition]
•
When the next serial reception is completed
while RDRF = 1
[Clearing condition]
•
When 0 is written to ORER after reading
ORER = 1
Rev. 1.00, 09/03, page 433 of 704
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