Figure 6.14 Bus Timing For 8-Bit, 2-State Data Access Space (Without Address Wait) - Renesas H8S/2437 Hardware Manual

Read Cycle Write Cycle
Address Data Address
Data
T T T T T T T T
1 2 3 4 1 2 3 4
AD15 to AD8
Address
Address
Data
Data
Note: n = 1 to 3

Figure 6.14 Bus Timing for 8-Bit, 2-State Data Access Space (Without Address Wait)

Rev. 1.00, 09/03, page 114 of 704