Timer I/O Control Register (Tior) - Renesas H8S/2437 Hardware Manual

12.3.3

Timer I/O Control Register (TIOR)

TIOR controls TGR. The TPU has a total of four TIOR registers, two for channel 0, and one each
for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and TIOR
operates as a buffer register.
• • • • TIORH_0, TIOR_1, TIOR_2
Bit Bit Name Initial Value
7 IOB3 0
6 IOB2 0
5 IOB1 0
4 IOB0 0
3 IOA3 0
2 IOA2 0
1 IOA1 0
0 IOA0 0
• • • • TIORL_0
Bit Bit Name Initial Value
7 IOD3 0
6 IOD2 0
5 IOD1 0
4 IOD0 0
3 IOC3 0
2 IOC2 0
1 IOC1 0
0 IOC0 0
Rev. 1.00, 09/03, page 310 of 704
R/W Description
R/W I/O Control B3 to B0
R/W Specify the function of TGRB.
R/W
R/W
R/W I/O Control A3 to A0
R/W Specify the function of TGRA.
R/W
R/W
R/W Description
R/W I/O Control D3 to D0
R/W Specify the function of TGRD.
R/W
R/W
R/W I/O Control C3 to C0
R/W Specify the function of TGRC.
R/W
R/W