Renesas H8S/2437 Hardware Manual page 246

• PB4/TMI1_1/HSYNCI_1
According to the setting of the PB4DDR bit, the pin function is switched as shown below.
When the external clock is selected by the CKS2 to CKS0 bits in TCR of the TMR1_1, this pin
functions as the TMCI1_1 input pin. When the CCLR1 and CCLR0 bits in TCR of the
TMR1_1 are all set to 1, this pin functions as the TMRI1_1 input pin. When the SIMOD1 bit
(IHI signal) in TCONRI of the timer connection_1 is set to 1, this pin functions as the
HSYNCI_1 input pin.
PB4DDR
Pin function
• PB3/FTIA_1/VSYNCI_1
According to the setting of the PB3DDR bit, the pin function is switched as shown below.
When the ICIAE bit in TIER of the FRT_1 is set to 1, this pin functions as the FTIA_1 input
pin. When the SIMOD1 and SIMOD0 bits (IVI signal) in TCONRI of the timer connection_1
are all set to 1, this pin functions as the VSYNCI_1 input pin.
PB3DDR
Pin function
• PB2/FTID_1/CSYNCI_1
According to the setting of the PB2DDR bit, the pin function is switched as shown below.
When the ICIDE bit in TIER of the FRT_1 is set to 1, this pin functions as the FTID_1 input
pin. When the SIMOD1 and SIMOD0 bits (IHI signal) in TCONRI of the timer connection_1
are set to 01, this pin functions as the CSYNCI_1 input pin.
PB2DDR
Pin function
Rev. 1.00, 09/03, page 208 of 704
0
PB4 input pin
TMI1_1 input pin
HSYNCI_1 input pin
0
PB3 input pin
FTIA_1 input pin
VSYNCI_1 input pin
0
PB2 input pin
FTID_1 input pin
CSYNCI_1 input pin
1
PB4 output pin
1
PB3 output pin
1
PB2 output pin