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φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1)(3) Reset exception-handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception-handling vector address)
(5)
Start address ((5)=(2)(4))
(6)
First program instruction
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
On-Chip Peripheral Functions after Reset Release
After reset release, the module stop control register (MSTPCR, EXMSTPCR) is initialized and all
modules enter module stop mode.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.
Rev. 1.00, 09/03, page 60 of 704
Vector fetch
(1)
(2)
Figure 4.1 Reset Sequence
Prefetch of first
Internal
program instruction
processing
(3)
High
(4)
(5)
(6)
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