Table of Contents
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7.10.2 Port 9 Data Register (P9DR)................................................................................190
7.10.3 Port 9 Register (PORT9)......................................................................................190
7.10.4 Port Function Control Register (PFCR) ...............................................................191
7.10.5 Pin Functions .......................................................................................................192
7.11 Port A ................................................................................................................................198
7.11.1 Port A Data Direction Register (PADDR) ...........................................................198
7.11.2 Port A Data Register (PADR) ..............................................................................199
7.11.3 Port A Register (PORTA) ....................................................................................199
7.11.4 Pin Functions .......................................................................................................200
7.12 Port B ................................................................................................................................205
7.12.1 Port B Data Direction Register (PBDDR)............................................................205
7.12.2 Port B Data Register (PBDR) ..............................................................................206
7.12.3 Port B Register (PORTB) ....................................................................................206
7.12.4 Pin Functions .......................................................................................................207
7.13 Port C ................................................................................................................................210
7.13.1 Port C Data Direction Register (PCDDR)............................................................210
7.13.2 Port C Data Register (PCDR) ..............................................................................210
7.13.3 Port C Register (PORTC) ....................................................................................211
7.13.4 Pin Functions .......................................................................................................211
7.14 Change of Peripheral Function Pins..................................................................................214
7.14.1 Port Control Register 0 (PTCNT0) ......................................................................214
7.14.2 Port Control Register 1 (PTCNT1) ......................................................................215
7.14.3 Port Control Register 2 (PTCNT2) ......................................................................216
Section 8 8-Bit PWM Timer (PWM)................................................................ 217
8.1
Features .............................................................................................................................217
8.2
Input/Output Pin................................................................................................................218
8.3
Register Descriptions ........................................................................................................218
8.3.1
PWM Register Select (PWSL).............................................................................219
8.3.2
PWM Data Registers 7 to 0 (PWDR7 to PWDR0) ..............................................220
8.3.3
PWM Data Polarity Register (PWDPR) ..............................................................221
8.3.4
PWM Output Enable Register (PWOER) ............................................................221
8.3.5
Peripheral Clock Select Register (PCSR) ............................................................222
8.4
Operation...........................................................................................................................223
Section 9 14-Bit PWM Timer (PWMX)........................................................... 225
9.1
Features .............................................................................................................................225
9.2
Input/Output Pins ..............................................................................................................226
9.3
Register Descriptions ........................................................................................................226
9.3.1
PWMX (D/A) Counters H and L (DACNTH and DACNTL) .............................227
9.3.2
PWMX (D/A) Data Registers A and B (DADRA and DADRB).........................228
9.3.3
PWMX (D/A) Control Register (DACR).............................................................230
9.3.4
Peripheral Clock Select Register (PCSR) ............................................................231
Rev.1.00, 09/03, page xiii of xxxviii
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