Figure 17.15 Sample Flowchart For Master Receive Mode - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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Master receive mode
Clear TEND in ICSR
Set TRS = 0 (ICCRA)
Clear TDRE in ICSR
Set ACKBT = 0 (ICIER)
Dummy reading of ICDRR
Read RDRF in ICSR
No
RDRF = 1 ?
Yes
(Last receive
1)?
No
Read ICDRR
Set ACKBT = 1 (ICIER)
Set RCVD = 1 (ICCRA)
Read ICDRR
Read RDRF in ICSR
No
RDRF = 1 ?
Yes
Clear STOP in ICSR
Write BBSY = 0
and SCP = 0
Read STOP in ICSR
No
STOP = 1 ?
Yes
Read ICDRR
Set RCVD = 0 (ICCRA)
Set MST = 0 (ICCRA)
End

Figure 17.15 Sample Flowchart for Master Receive Mode

Rev. 1.00, 09/03, page 502 of 704
[1]
Clear TEND, set master receive mode, and then clear TDRE.*
[2]
Set acknowledge to the transmit device.*
[1]
[3]
Dummy reading of ICDDR*
[4]
Wait for 1 byte to be received.
[2]
[5]
Check if (last receive
[3]
[6]
Read the receive data.
[7]
Set acknowledge of the last byte. Disable continuous reception (RCVD = 1).
[4]
[8]
Read receive data of (last byte
[9]
Wait for the last byte to be received.
Yes
[5]
[10] Clear STOP flag.
[6]
[11] Stop condition issuance
[12] Wait for the generation of stop condition.
[13] Read the receive data of the last byte.
[7]
[14] Clear RCVD to 0.
[15] Set slave receive mode.
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Note:
*
Steps 1 to 3 should be executed
continously.
1).
1).

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