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2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
2.4.3
Extended Register (EXR)
EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC
instructions. When these instructions except for the STC instruction is executed, all interrupts
including NMI will be masked for three states after execution is completed.
Bit
Bit Name Initial Value R/W
7
T
6 to 3
2
I2
1
I1
0
I0
SP (ER7)
Figure 2.8 Stack
0
R/W
All 1
1
R/W
1
R/W
1
R/W
Description
Trace Bit
When this bit is set to 1, a trace exception-handling is
started each time an instruction is executed. When
this bit is cleared to 0, instructions are executed in
sequence.
Reserved
These bits are always read as 1.
These bits designate the interrupt mask level (0 to 7).
For details, refer to section 5, Interrupt Controller.
Free area
Stack area
Rev. 1.00, 09/03, page 25 of 704
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