Bus Interface; Data Size And Data Alignment; Figure 6.3 Access Sizes And Data Alignment Control (8-Bit Access Space) - Renesas H8S/2437 Hardware Manual

6.5

Bus Interface

The normal extended bus interface enables direct connection between the ROM and SRAM. For
details on the basic area and areas 1 to 3 bus specification selection, refer to tables 6.2 and 6.3.
For multiplex extended bus interface, only products compatible with this bus system can be
directly connected. For details on areas 1 to 3 bus specification selection, refer to tables 6.4 to 6.6
6.5.1

Data Size and Data Alignment

Data sizes for the CPU are byte, word, and longword. The BSC has a data alignment function, and
controls whether the upper data bus (D15 to D8/AD15 to AD8) or lower data bus (D7 to D0/AD7
to AD0) is used when the external address space is accessed, according to the bus specifications
for the area being accessed (8-bit access space or 16-bit access space) and the data size. The
multiplex extended address cycle is fixed to the bus specifications of the area being accessed (8-bit
access space or 16-bit access space).
8-Bit Access Space:
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8/AD15 to AD8) is always used for accesses. The amount of data that
can be accessed at one time is one byte. A word access is performed as two byte accesses, and a
longword access, as four byte accesses.
Byte size
Word size
Longword
size

Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)

Rev. 1.00, 09/03, page 102 of 704
D15/
AD15
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Upper data bus
D8/ D7/
AD8 AD7
Lower data bus
D0/
AD0