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Notes:
1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used.
Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC
and AVref pins by connection to the power supply (VCC). The relationship between these two pins
should be AVref ≤ AVCC.
2. P80/SCL0 to P83/SDA1 and PC0/SCL2 to PC3/SDA3 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 to SCL3 and
SDA0 to SDA3 (ICE bit in ICCRA is 1).
P80 to P83 and PC0 to PC3 (ICE bit in ICCRA is 0) high levels are driven by NMOS. An external
pull-up resistor is necessary to provide high-level output from these pins when they are used as an
output.
3. Current consumption values are for V
unloaded and the on-chip pull-up MOSs in the off state.
4. The values are for V
5. Except for flash memory programming/erasing.
Table 24.3 Permissible Output Currents
Conditions: V
= 3.0 V to 3.6 V, V
CC
Item
Permissible output low
current (per pin)
Permissible output low
current (total)
Permissible output
high current (per pin)
Permissible output
high current (total)
Notes: 1. To protect LSI reliability, do not exceed the output current values in table 24.3.
2. When driving a Darlington transistor directly, always insert a current-limiting resistor in
the output line, as shown in figure 24.1.
Figure 24.1 Darlington Transistor Drive Circuit (Example)
Rev. 1.00, 09/03, page 672 of 704
IH
≤ VCC < 3.0 V, V
RAM
= 0 V
SS
SCL0 to SCL3, SDA0 to
SDA3
All output pins
Total of all output pins
All output pins
Total of all output pins
This LSI
Port
min. = VCC – 0.2 V and V
min. = VCC – 0.2 V, and V
IH
Symbol Min.
I
OL
∑I
OL
–I
OH
∑–I
OH
2 kΩ
Darlington transistor
max. = 0.2 V with all output pins
IL
max. = 0.2 V.
IL
Typ.
Max.
10
2
60
2
30
Unit
mA
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