Table of Contents
Advertisement
6.4
Bus Control
6.4.1
Bus Specifications
The external address space bus specifications consist of three elements: bus width, number of
access states, and the number of wait modes and program wait states. The bus width and number
of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the
bus controller.
Normal Extended Mode:
1. Bus Width
A bus width of 8 or 16 bits can be selected with the ABWn bit in BCRAn.
2. Number of Access States
The number of access states for data access , 2-state or 3-state can be selected with the ASTn
bit in BCRAn. When 2-state access space is designated, wait state insertion is disabled.
3. Wait Mode and Number of Program Wait States
When 3-state access space is designated by the ASTn bit in BCRAn, the number of program
wait states to be inserted automatically is selected with WMSn1, WMSn0, WCn1, and WCn0
in the BCRAn. From 0 to 3 program wait states can be selected.
The external extended wait function is effective when the low-speed device is connected to the
external address area.
For details on normal extended address range, external address area, as well as bus interface
specifications, refer to tables 6.2 and 6.3.
Table 6.2
Address Range and External Address Area (Normal Extended Mode)
Address Range
H'080000 to H'FBFFFF (15 Mbytes)
H'FC0000 to H'FCFFFF (64 kbytes)
H'FD0000 to H'FDFFFF (64 kbytes)
H'FE0000 to H'FEFFFF (64 kbytes)
H'FF0000 to H'FF9FFF (40 kbytes)
Area
Basic area (shares bus specification with area 1)
Area 1
Area 2
Area 3
Integrated with basic area when RAME = 0
Rev. 1.00, 09/03, page 97 of 704
Advertisement
Table of Contents
