Timer Mode Register (Tmdr); Table 12.7 Tpsc2 To Tpsc0 (Channel 2) - Renesas H8S/2437 Hardware Manual

Table 12.7 TPSC2 to TPSC0 (Channel 2)

Bit 2
Channel TPSC2
2 0
1
Note: This setting is ignored when channel 2 is in phase counting mode.
12.3.2

Timer Mode Register (TMDR)

TMDR sets the operating mode for each channel. The TPU has a total of three TMDR registers,
one for each channel. TMDR settings should be made only when TCNT operation is stopped.
Bit Bit Name Initial Value R/W
7, 6 — All 1
5 BFB 0
Rev. 1.00, 09/03, page 308 of 704
Bit 1 Bit 0
TPSC1 TPSC0
0 0
1
1 0
1
0 0
1
1 0
1
Description
— Reserved
These bits are always read as 1 and cannot be modified.
R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal way,
or TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register,
TGRD input capture/output compare is not generated. In
channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Description
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on φ/1024