Renesas H8S/2437 Hardware Manual page 27

Figure 12.42 TGI Interrupt Timing (Input Capture) ...................................................................355
Figure 12.43 TCIV Interrupt Setting Timing..............................................................................355
Figure 12.44 TCIU Interrupt Setting Timing..............................................................................356
Figure 12.45 Timing for Status Flag Clearing by CPU...............................................................356
Figure 12.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................357
Figure 12.47 Contention between TCNT Write and Clear Operations .......................................358
Figure 12.48 Contention between TCNT Write and Increment Operations ...............................358
Figure 12.49 Contention between TGR Write and Compare Match...........................................359
Figure 12.50 Contention between Buffer Register Write and Compare Match ..........................359
Figure 12.51 Contention between TGR Read and Input Capture ...............................................360
Figure 12.52 Contention between TGR Write and Input Capture ..............................................360
Figure 12.53 Contention between Buffer Register Write and Input Capture..............................361
Figure 12.54 Contention between Overflow and Counter Clearing............................................362
Figure 12.55 Contention between TCNT Write and Overflow...................................................362
Section 13 Timer Connection
Figure 13.1 Schematic Diagram of Timer Connection ...............................................................366
Figure 13.2 Block Diagram of Timer Connection ......................................................................367
Figure 13.3 Block Diagram for PWM Decoding ........................................................................380
Figure 13.4 Timing Chart for PWM Decoding...........................................................................381
Figure 13.5 Block Diagram for Clamp Waveform Generation...................................................383
Figure 13.6 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) ...............383
Figure 13.7 Timing Chart for Clamp Waveform Generation (CL3 Signal)................................384
Figure 13.8 Block Diagram for Measurement of 8-Bit Timer Divided Waveform Period .........385
Figure 13.9 Timing Chart for Measurement of IVI Signal and
IHI Signal Divided Waveform Periods ...................................................................386
Figure 13.10 Block Diagram for 2fH Modification of IHI Signal ..............................................388
Figure 13.11 2fH Modification Timing Chart ............................................................................389
Figure 13.12 Block Diagram for IVI Signal Fall Modification and IHI Signal Operation .........390
Figure 13.13 Fall Modification and IHI Synchronization Timing Chart ....................................391
Figure 13.14 Block Diagram for IVG Signal Generation ...........................................................392
Figure 13.15 Block Diagram for IHG Signal Generation ...........................................................393
Figure 13.16 IVG Signal/IHG Signal/CL4 Signal Timing Chart................................................395
Figure 13.17 CBLANK Output Waveform Generation ..............................................................398
Section 14 Duty Measurement Circuit
Figure 14.1 Block Diagram of Duty Measurement Circuit.........................................................400
Figure 14.2 Example of Duty Measurement for External Event Signal .....................................406
Figure 14.3 TWCNT Count Timing ...........................................................................................407
Figure 14.4 TWCNT Clear Timing by Setting START Bit........................................................407
Figure 14.5 Count Start Timing for Duty Measurement.............................................................408
Figure 14.6 Input Capture Timing during Duty Measurement ...................................................408
Figure 14.7 Clear Timing for START Bit when Duty Measurement Ends.................................409
Figure 14.8 Set Timing for Duty Measurement End Flag (ENDF).............................................409
Rev. 1.00, 09/03, page xxvii of xxxviii