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Initial
Bit
Bit Name
Value
31 to 16
15 to 0 F15 to F0
(b) Flash Pass/Fail Parameter (FPFR: General Register R0L of CPU)
FPFR indicates the return value of the initialization result.
Rev. 1.00, 09/03, page 544 of 704
R/W
Description
Unused
These bits should be cleared to 0.
R/W
Frequency Set
Set the operating frequency of the CPU. With the PLL
multiplication function, set the frequency multiplied. The
setting value must be calculated as the following
methods.
•
The operating frequency which is shown in MHz units
must be rounded a number to three decimal places
and be shown in a number of two decimal places.
•
The value multiplied by 100 is converted to the binary
digit and is written to FPEFEQ (general register
ER0).
For example, when the operating frequency of the CPU
is 20.000 MHz, the value is as follows.
•
The number to three decimal places of 20.000 is
rounded and the value is thus 20.00.
•
The formula that 20.00 × 100 = 2000 is converted to
the binary digit and B'0000, B'0111, B'1101, and
B'0000 (H'07D0) are set to ER0.
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