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16.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 16.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and BRR can be read from or
written to by the CPU at all times.
Table 16.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous mode
Clocked synchronous
mode
Smart card interface
mode
Notes: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following table.
SMR Setting
CKS1
0
0
1
1
Table 16.3 shows sample N settings in BRR in normal asynchronous mode. Table 16.4 shows the
maximum bit rate settable for each operating frequency. Table 16.6 shows sample N settings in
BRR in clocked synchronous mode. Tables 16.5 and 16.7 show the maximum bit rates with
external clock input.
Rev. 1.00, 09/03, page 436 of 704
Bit Rate
φ × 10
6
B =
2n – 1
64 × 2
× (N + 1)
φ × 10
6
B =
2n – 1
8 × 2
× (N + 1)
φ × 10
6
B =
2n + 1
S × 2
× (N + 1)
CKS0
n
0
0
1
1
0
2
1
3
Error
φ × 10
Error (%) = {
B × 64 × 2
{
Error (%) =
B × S × 2
SMR Setting
BCP1
BCP0
0
0
0
1
1
0
1
1
6
– 1 } × 100
2n – 1
× (N + 1)
φ × 10
6
}
–1 × 100
2n + 1
× (N + 1)
S
32
64
372
256
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