Figure 6.11 Bus Timing For 16-Bit, 3-State Access Space (Odd Byte Access) - Renesas H8S/2437 Hardware Manual

Bus cycle
T T T
1 2 3
Address bus
D15 to D8
Read Invalid
D7 to D0
Valid
High
Write
Undefined
D15 to D8
D7 to D0
Valid
Note: n = 1 to 3

Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)

Rev. 1.00, 09/03, page 111 of 704